This invention relates to programmable controllers and to integrated circuits for interfacing peripheral devices to computers.
There are a number of peripheral interface controller chips known in the art. Such devices typically include a data bus for receiving data or commands from a host CPU, and an address bus for receiving an address from the host CPU. The received data (or command) is placed in an appropriate register selected in response to the received address. The controller then sends appropriate commands or data to the peripheral device in response to the data or command received from the host CPU. Such controllers can control peripheral I/O devices so that the host CPU need not spend time performing peripheral device control tasks.
As peripheral devices become faster, it is necessary to provide controllers capable of great speed and efficiency. Accordingly, it is an object of the present invention to provide a controller capable of performing a number of tasks in parallel to enhance controller speed and efficiency.